01 · Template gallery模板画廊

Fourteen templates,
drawn in glass. 十四张模板，
画在玻璃上。

Every diagram genre glass-design ships as a copy-ready template — from architecture, flow and sequence to SoC block, timing waveform, ring buffer and scheduler timeline. Paste one into a glass page, drop the preview style, and the page's tokens take over both themes. glass-design 把每种图型都做成可直接复制的模板——从架构、流程、时序，到 SoC 框图、时序波形、环形缓冲、调度时间线。把它贴进 glass 页面、删掉预览样式，页面的 token 就会接管双主题配色。

02 · Featured主图

The architecture template. 架构模板。

templates/diagrams/architecture.svg · 1240 × 440
01 · EDGE 02 · INGEST 03 · INDEX 04 · SERVE SDK · 14 langs OTel collector Edge batcher Replay uploader apps and services drop-in pipeline 4ms coalescing backfill history Regional ingest gateways · 6 regions 2.4M events/s sustained · at-least-once into the log · backpressure to the edge LIVE Hot tier — in memory last 48h · columnar · sub-ms scans Cold tier — object storage 410TB · 12× zstd · lazily promoted Query engine — vectorized, scatter-gather 38MS P99 OVER A TRILLION ROWS Streaming render diffs over the wire · 60fps charts
Twelve nodes, four tiers, one strong-stroked focus. Delete the embedded preview style when you paste it — the page's .glass-svg classes carry both themes. 十二个节点、四层结构、一个强描边焦点。贴进页面时删掉内嵌预览样式——页面的 .glass-svg 类会扛起双主题。
03 · The classic six经典六张

Six genres, one material. 六种图型，一种材质。

templates/diagrams/flow.svg
App SDK Edge batch Region log emit + tag 4ms window at-least-once EVENT LEAVES THE PROCESS IN UNDER 1MS BACKPRESSURE FLOWS RIGHT TO LEFT
Three nodes and two cyan hops — the smallest flow that still says where energy goes. Start here for any left-to-right pipeline. 三个节点、两段 cyan 连线——能说清能量去向的最小流程图。任何从左到右的管线都从它起步。
templates/diagrams/sequence.svg
Client Planner Regions ×6 SQL scatter ×6 partials 38MS P99 merge + sort
Lifelines are hairlines, the reply is dashed, and the one accent label marks the latency that matters. 生命线就是发丝线，回包用虚线，唯一的 accent 标签标出真正要紧的延迟。
templates/diagrams/state-machine.svg
baseline candidate firing resolved 3σ × 4MIN HUMAN PAGED BACK IN BAND RELEARN
Pill-shaped states, dashed return edges, mono guards on every transition — only the firing state takes the strong stroke. 药丸形状态、虚线回边、每条迁移都带 mono 守卫——只有 firing 态拿到强描边。
templates/diagrams/timeline.svg
T+0 T+15M T+45M T+90M canary 1% wave 25% wave 75% full fleet auto-diff vs baseline error budget watch latency gate marker on charts ANY GATE FAILS → AUTO-ROLLBACK IN 40S
One hairline, four stops; the cyan tick marks the moment a human last touched it. 一条发丝线、四个停靠点；cyan 刻度标记人手最后碰过的时刻。
templates/diagrams/bitfield.svg
128-BIT HEADER · LITTLE ENDIAN timestamp stream id shard flags crc 48 32 16 16 16 payload — column-coded key/value pairs SHARD FIELD ROUTES WITHOUT PARSING THE PAYLOAD
Bit cells keep square corners on purpose — adjacent fields read as one 128-bit word, and the routed field is the only lit one. 位格刻意不做圆角——相邻字段读起来是同一个 128 位字，被路由读取的字段是唯一点亮的。
templates/diagrams/build-pipeline.svg
commit unit ×3k e2e ×140 image sign + deploy MEDIAN COMMIT → FLEET · 22 MIN EVERY ARTIFACT SIGNED · SBOM ATTACHED
Fan out for the tests, fan back in for the artifact — the signed deploy node carries the strong stroke. 测试先扇出、再为产物收拢——签名发布节点带着强描边。
04 · The systems seven系统七张

Seven more, drawn for systems work. 再添七张，画给系统工程。

Hierarchy, control flow, deployment, silicon, signals, memory and scheduling — the denser genres run full-width so every label keeps its size, and the tint layer carries the categories: cyan for the hot path, indigo for storage and secondary lanes. 层级、控制流、部署、芯片、信号、内存、调度——更密的图型整行展开，每个标签都保住尺寸；类别交给着色层：cyan 是热路径，indigo 是存储与次级泳道。

templates/diagrams/hierarchy.svg · 1240 × 396
ONE COORDINATOR · FOUR WORKERS · FAN OUT, MERGE BACK Coordinator plans · delegates · merges partials Search · web Search · docs Analyse · data Analyse · code worker 1 · breadth queries worker 2 · internal corpus worker 3 · notebooks + SQL worker 4 · repo + traces search lane analysis lane PARTIALS MERGE BACK INTO ONE ANSWER
One coordinator, four workers, two tinted lanes — cyan searches, indigo analyses, and every partial result merges back into a single answer. 一个协调者、四个工作者、两条着色泳道——cyan 负责检索，indigo 负责分析，所有部分结果最终汇回同一个答案。
templates/diagrams/function-flowchart.svg · 1240 × 620
DRIVER PROBE · HAPPY PATH LEFT · ERROR LANE RIGHT platform_driver · drivers/misc/mydev.c mydev_probe(pdev) devm_kzalloc(ctx) ioremap registers request_irq(irq, isr) register chardev sizeof(*ctx) · GFP_KERNEL MMIO window · res->start IRQF_SHARED · dev_id = ctx misc_register(&ctx->mdev) ctx == NULL? base == NULL? ret < 0? yes yes yes no no no ERROR LANE · UNWIND IN REVERSE ret = -ENOMEM ret = -ENOMEM iounmap(base) ctx allocation failed MMIO map failed · nothing to unwind unwind the MMIO mapping, then return return 0 return ret EVERY ERROR RETURNS THROUGH ONE EXIT · UNWIND MIRRORS ACQUIRE ORDER
The happy path runs down the left in cyan; every failed check exits right into the indigo error lane and unwinds in reverse acquire order. 正常路径沿左侧 cyan 向下；每个失败的判断都向右退入 indigo 错误泳道，按申请的逆序回退。
templates/diagrams/deployment.svg · 1240 × 568
DEPLOYMENT TOPOLOGY · THREE ZONES prod · us-east primary 01 · EDGE anycast · 12 PoPs CDN WAF Load balancer edge cache · 98% hit managed rules · v34 least-conn · TLS terminate 02 · APP CLUSTER auto-scale 2-8 nodes api worker scheduler REST + SSE · stateless queue consumer · retries cron + backoff ×3 ×5 dispatch 03 · DATA encrypted at rest · PITR Postgres 16 Redis Object store primary + 2 replicas queues · hot cache artifacts · 410TB THE REQUEST PATH CROSSES THREE ZONES · ONLY THE DATA ZONE HOLDS STATE hot request path stateful zone
Three zones, one stateful: the cyan request path ends at Postgres, and only the indigo data zone is allowed to remember anything. 三个区域，只有一个有状态：cyan 请求路径终点是 Postgres，只有 indigo 数据区被允许记住任何东西。
templates/diagrams/soc-block.svg · 1240 × 600
QUARTZ-3550 SOC · BLOCK DIAGRAM arm64 · 12nm LP · 0.8V core rail clk · rst 01 02 CPU SUBSYSTEM DynamIQ · 1.8GHz Cortex-A55 ×2 L2 · 512K GIC-600 L1 32K I/D per core unified · ECC interrupt distributor CLOCK & RESET 24MHz xtal PLL ×3 CRU core · ddr · peri gate · reset AXI NoC · 64-bit @ 800MHz system interconnect · QoS arbitration · 4 masters APB bridge AXI-to-APB · 100MHz MEMORY AXI slaves DDR4 ctrl + PHY SRAM 256K Boot ROM DDR4-3200 · 32-bit + ECC scratch 64K mask HIGH-SPEED PERIPH DMA masters PCIe Gen3 ×2 USB 3.0 GbE MAC root complex · MSI-X xHCI DRD RGMII · TSO LOW-SPEED PERIPH via APB UART ×4 I2C ×3 SPI ×2 GPIO 16550A 400kHz FM mode 0-3 4 banks ×32 MAIN DATA PATH · CPU → NOC → DDR4 · EVERYTHING ELSE HANGS OFF THE FABRIC
The cyan-tinted CPU subsystem reaches the indigo memory zone through the one strong-stroked NoC — the two numbered hops are the whole main data path. cyan 着色的 CPU 子系统经由唯一强描边的 NoC 抵达 indigo 内存区——两个编号跳点就是整条主数据通路。
templates/diagrams/protocol-stack.svg · 1240 × 560
PROTOCOL LAYERING · PEER VIEW peer agreement · no wire the only real wire this transfer TRANSACTION LAYER TRANSACTION LAYER DATA LINK LAYER DATA LINK LAYER PHYSICAL LAYER PHYSICAL LAYER requester completer TLP generator builds header + payload Flow control credit based TLP parser decodes header Flow control returns credits Seq num + LCRC one per packet Replay buffer holds until ACK LCRC check drops on mismatch ACK / NAK gen a DLLP, never a TLP 128b/130b + scrambler block sync TX driver differential pair Descrambler + decode recovers symbols RX equalizer CDR + de-emphasis TLP · end to end DLLP · hop by hop no line here either the real one runs below PCIe lane ×4 · 32 GT/s 1 2 3 4 5 6
The two dashed lines are agreements, not wires — nothing carries a TLP from one transaction layer straight to the other. The only bright solid line is the lane at the bottom; the cyan path 1–6 is the transfer itself. 两条虚线是约定，不是线——没有任何东西把 TLP 从一侧传输层直接送到另一侧。唯一那根亮实线是最底下的 lane；cyan 那条 1→6 才是这一笔传输。
templates/diagrams/address-map.svg · 1240 × 600
ADDRESS MAP · TWO VIEWPOINTS not DRAM direct mapping reclaim · this remap PCIe MMIO · 64-bit BAR windows of every device DRAM · reclaimed the gigabyte that was shadowed DRAM · direct 12 GiB MMIO hole PCI · LAPIC · IOAPIC · flash DRAM · direct 3 GiB, legacy region at the bottom DRAM 4 – 16 GiB reachable at its own address DRAM 3 – 4 GiB shadowed by the hole — needs a remap DRAM 0 – 3 GiB reachable at its own address SYSTEM PHYSICAL DIMM PHYSICAL · 16 GiB 0x40_0000_0000 TOUUD 0x4_4000_0000 REMAPBASE 0x4_0000_0000 0x1_0000_0000 TOLUD 0xC000_0000 0x0000_0000 TOM 16G 4G 3G 0x0 direct direct reclaim · same DRAM segment heights are not to scale · low addresses at the bottom
Leaders point at boundaries, never into a region — a boundary is an address, a region is a range. Symbol names in sans, literal constants in mono. The cyan line is the point: the gigabyte hidden under the MMIO hole reappears above TOUUD. 引线指的是边界，不是区域——边界是一个地址，区域是一段范围。符号名走 sans，字面常量走等宽。cyan 那条线是全图的结论：藏在 MMIO 空洞下的那 1 GiB，在 TOUUD 之上重新露面。
templates/diagrams/glyphs.svg · 1240 × 470 · a sheet, not a figure
GLYPH SHEET · COPY ONE <g> AT A TIME QUEUE finite depth, in order BYTE STREAM serialized bytes, not addresses SLOTS a place something plugs into PORT TAB an interface owned by this die DEVICE CARD pluggable board · model text, no logo AC COUPLING a capacitor, not “isolation” SYNC clock-domain crossing only HATCH a window onto another space out in TLP header + payload PCIe ×16 slots Host CPU die 64 core IMC 200 GbE NIC 2 × QSFP56 D+ D− sync clk A clk B BAR0 window
A rounded rectangle can stand for anything, so it says nothing. Each glyph is a noun with one fixed meaning; draw one where the thing is not there and the figure states something false. Cyan marks the one live state per glyph. 一个圆角矩形能代表任何东西，所以它什么也没说。每个字形都是意义固定的名词；在没有那样东西的地方画上它，就是在图上写了一句假话。cyan 每个字形只点一处"活着"的状态。
templates/diagrams/interconnect-map.svg · 1240 × 640
MULTI-DIE INTERCONNECT · ADDRESS MAP window onto the other space direct ld / st path NODE 0 · SOCKET one coherent domain NODE 1 · SOCKET one coherent domain DDR5 Host CPU die Accelerator die DDR5 Host CPU die Accelerator die 512 GB 64 core · 2.4 GHz 96 GB HBM3 · on-package 512 GB 64 core · 2.4 GHz 96 GB HBM3 · on-package DDR5 · 8 ch DDR5 · 8 ch CXL 3.0 · 64 GB/s CXL 3.0 · 64 GB/s fabric · 400 GB/s fabric · 400 GB/s Fabric switch 8 port · non-blocking CPU core · ld / st Accel core · ld / st HOST PHYSICAL ADDRESS SPACE DEVICE PHYSICAL ADDRESS SPACE DDR5 · 512 GB Accel HBM window MMIO 0x0000_0000 0x80_0000_0000 HBM3 · 96 GB Host DDR window reserved 0x0000_0000 0x18_0000_0000 CXL.mem · HDM decoder
Topology above, one address space per viewpoint below, and the cyan path carrying the whole point: a CPU core reaches the hatched accelerator window with a plain store, so a pointer crosses without a copy. The two strips never merge — the same DRAM is 0x80_0000_0000 to the host and 0x18_0000_0000 to the device. Segment widths are not to scale. 上半是拓扑，下半是每个视角各一条地址空间，那条 cyan 路径就是全图的结论：CPU 核用一条普通 store 就写得到斜纹那一段，指针可以直接递过去，不用拷贝。两条带永不合并——同一块 DRAM 在 host 眼里是 0x80_0000_0000，在设备眼里是 0x18_0000_0000。段宽不按比例。
templates/diagrams/hw-timing-waveform.svg · 1240 × 440
SPI MODE 0 · CPOL=0 CPHA=0 · JEDEC ID READ MX25L6433F · SCLK 25MHz command phase · MOSI drives data phase · MISO drives SCLK CS_N MOSI MISO 0x9F 0x00 0xC2 0x20 tCSS tSU ≥ 5ns t0 t1 t2 t3 t4 t5 t6 t7 host drives device drives high-Z · not driven sampling edge · SCLK rising BIT PERIOD 40NS
Cyan cells are what the host drives, indigo cells are the device's reply, and every dotted line is an SCLK rising edge doing the sampling. cyan 数据格是主机驱动的内容，indigo 数据格是器件的应答，每条点线都是一个负责采样的 SCLK 上升沿。
templates/diagrams/algorithm-ringbuffer.svg · 1240 × 344
kfifo ring buffer struct kfifo · buf[16] · mask = size - 1 = 0x0F include/linux/kfifo.h · size is a power of two out (tail) consumer reads in (head) producer writes 5A 6B 0D 31 9C E2 47 012 345 678 91011 121314 15 wrap: idx & (size - 1) kfifo_in(fifo, buf, len) copy to buf[in & mask] · smp_wmb() · in += len kfifo_out(fifo, buf, len) smp_rmb() · copy from buf[out & mask] · out += len len = in - out = 7 valid data free
Seven indigo slots of valid data sit between two pointers — the cyan in pointer writes, the mask wraps, and no byte ever moves. 两个指针之间是七格 indigo 有效数据——cyan 的 in 指针负责写入，mask 负责回绕，数据本身从不搬家。
templates/diagrams/sched-timeline.svg · 1240 × 400
SCHED · CFS RUN VIEW · 12MS WINDOW trace-cmd record -e sched_switch -e sched_migrate_task IRQ · eth0 rx CPU 0 CPU 1 CPU 2 app: render kworker/u8 kworker/u8 kworker/u8 app: render irq/eth0 idle idle idle idle idle idle idle preempted at 4ms migrate · load balance 0 2 4 6 8 10 12 ms app: render · CFS task kworker/u8 · workqueue irq/eth0 · threaded IRQ bare lane = idle
One render task, three CPUs: preempted by the strong-stroked IRQ at 4ms, then moved by the load balancer — the dashed cyan arc is the migration. 一个渲染任务、三个 CPU：4ms 处被强描边的 IRQ 抢占，随后被负载均衡挪走——cyan 虚线弧就是那次迁移。
05 · Silicon & code芯片与代码

Seven more, drawn for silicon. 再添七张，画给芯片。

Board topology over its own address bar, a tile mesh, a gate-level datapath, layered encapsulation on a byte ruler, an annotated console, a pointer graph and a bus fabric. Cyan stays reserved for the one thing being traced — the mesh rails and the ring stops drop to the neutral line token so that reservation still means something. 板级拓扑压在自己的地址条上、瓦片网格、器件级数据通路、字节标尺上的逐层封装、终端实录标注、指针图、总线挂载。cyan 只留给被追踪的那一样——互连轨和站点降到中性线条 token，这个约定才还算数。

templates/diagrams/system-topology.svg · 1120 × 560
SYSTEM TOPOLOGY · PCIe HIERARCHY OVER ITS ADDRESS SPACE DRAM device MMIO window owns this BAR DDR4 · 2 DIMM DDR4 · 2 DIMM ch0 · 3200 MT/s ch1 · 3200 MT/s ch2 · 3200 MT/s ch3 · 3200 MT/s SoC PACKAGE one coherent domain IMC IMC Core 0Core 1 Core 2Core 3 ROOT COMPLEX · BUS 00 RP0 · 00:1c.0 RP1 · 00:1c.4 RP2 · 00:1d.0 Gen4 x4 · BUS 01 Gen4 x8 · BUS 02 Gen3 x1 · BUS 06 x4 · BUS 03 x4 · BUS 04 PCIe SWITCH 1 upstream · 2 downstream · BUS 02 NVMe SSDAccelerator GPUNetwork 01:00.0 · BAR0 16 KiB 03:00.0 · BAR0 256 MiB 04:00.0 · BAR0 512 MiB 06:00.0 · BAR0 128 KiB DRAM · 0 – 2 GiB nvme accel gpu nic DRAM · 4 GiB and up 0x0000_0000 PCI MMIO window · 32-bit 0x1_0000_0000 not to scale
The PCIe tree and the physical address space in one frame. Every wire carries its link width and bus number, every device card its BDF and BAR size, and a dashed leader drops from each card onto its own segment of the bar. Split these into two figures and the reader has to hold the mapping in their head — which is exactly the part that goes wrong. PCIe 树和物理地址空间画在同一张图里。每根线标接口宽度和总线号，每张设备卡标 BDF 和 BAR 大小，虚线引线从卡落到地址条上属于它的那一段。拆成两张图，读者就得自己在脑子里做这个映射——而出错的恰恰是这一步。
templates/diagrams/die-floorplan.svg · 1120 × 560
DIE FLOORPLAN · TILE MESH core cache slice IO tile mesh · ring stop this request UPI ×20 2 links · 10.4 GT/s PCIe ×16 Gen5 · 32 GT/s DMI ×8 to PCH PCIe ×16 Gen5 · 32 GT/s CHA · LLC 3 MiB Core 0 CHA · LLC 3 MiB Core 1 CHA · LLC 2 MiB Core 2 CHA · LLC 3 MiB Core 3 CHA · LLC 2 MiB Core 4 CHA · LLC 2 MiB Core 5 CHA · LLC 3 MiB Core 6 CHA · LLC 3 MiB Core 7 CHA · LLC 2 MiB Core 8 CHA · LLC 3 MiB Core 9 CHA · LLC 3 MiB Core 10 CHA · LLC 2 MiB Core 11 CHA · LLC 3 MiB Core 12 CHA · LLC 3 MiB Core 13 CHA · LLC 2 MiB Core 14 CHA · LLC 2 MiB Core 15 CHA · LLC 3 MiB Core 16 CHA · LLC 2 MiB Core 17 CHA · LLC 3 MiB Core 18 CHA · LLC 3 MiB Core 19 MC 0 MC 1 DDR5 · 3 ch DDR5 · 3 ch 1 2 3 COMPUTE DIE · 20 tiles · 5 × 4 mesh a tile joins the mesh at its ring stop, not at its edge
Twenty tiles, each a core under its own cache slice, joined by mesh rails whose crossings are the ring stops. A tile joins the mesh at its stop, not at its edge — that distinction is why one request's latency depends on how many stops it crosses. Badges 1 to 3 trace a single miss out to the memory controller. 二十块瓦片，每块是一个核加它自己那片缓存，瓦片之间跑互连轨，交叉点就是站点。瓦片挂在自己的站点上、不是连在轨边上——一次访问的延迟取决于跳了几站，靠的就是这个区别。徽章 1–3 追一次未命中一路走到内存控制器。
templates/diagrams/datapath.svg · 1120 × 560
DATAPATH · 4-WAY SET-ASSOCIATIVE LOOKUP comparator multiplexer OR gate 4712 116 50 TAG · 36 bits SET INDEX · 6 BLOCK OFFSET · 6 6 → 64 decoder · one wordline per set 36 4 V · TAG ARRAY DATA ARRAY · SET 41 way 0 1 0x0004_A1C 64 B line · way 0 = way 1 0 0x00F1_2B8 64 B line · way 1 = way 2 1 0x0004_A1C 64 B line · way 2 = way 3 1 0x0091_7D0 64 B line · way 3 = 4:1 ≥1 word → load unit HIT a miss is this line staying low A B C D E way 1 is invalid, so its comparator can never assert — the valid bit is an input to the match, not a decoration
A four-way set-associative lookup drawn at gate level: the address splits, a decoder picks the set, four comparators race, and the match lines both drive the multiplexer and feed the OR gate that raises HIT. Way 1 is invalid, so its comparator can never assert — that one deliberate dead lane is what makes the valid bit legible. Badges A to E. 四路组相联查找画到器件一级：地址拆分、译码器选中一组、四个比较器同时比、匹配线一边驱动多路选择器一边进或门抬起 HIT。way 1 的 valid 是 0，它的比较器永远不会成立——故意留死这一路，valid 位才讲得清。徽章 A–E。
templates/diagrams/packet-encap.svg · 1120 × 560
PACKET ENCAPSULATION · ONE BYTE RULER, THREE LAYERS 8 px = 1 byte · bars are to scale with each other Transaction layer TLP header 16 B data payload 64 B 80 B · what the requester actually meant to send Data link layer the 80 B above, untouched + SeqNum 2 B + LCRC 4 B 86 B · replay needs the number, the receiver needs the CRC Physical layer · framing the 86 B above, untouched + STP 1 B + END 1 B 88 B · now it has a beginning and an end on the wire BYTE STRIPING · x4 LINK Lane 0 byte 0 byte 4 byte 8 Lane 1 byte 1 byte 5 byte 9 Lane 2 byte 2 byte 6 byte 10 Lane 3 byte 3 byte 7 byte 11 SerDes · 128b/130b · 32 GT/s per lane byte n leaves on lane n mod 4
One packet down three layers on a single byte ruler at eight pixels per byte, so each bar's width is its byte count. Two dashed guidelines pin the original eighty bytes: everything a lower layer adds appears outside them, never inside. Fields narrower than their own label get bracketed out to the margin rather than shrunk. 同一个报文走过三层，画在一把 8 px/字节的标尺上，所以每根条的宽度就是它的字节数。两条竖虚线钉住最初那 80 字节：下层加的东西一律长在外面，绝不进到里面。窄到装不下标签的字段用括线引到边上写，不缩字号。
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ANNOTATED CONSOLE · PCI ENUMERATION, ONE FAILING DEVICE real output, marked up · never retyped ttyS0 · 115200 8N1 · dmesg | grep -E 'pci|accel|nvme' [ 0.412903] PCI: MMCONFIG for domain 0000 [bus 00-ff] [ 0.418772] pci_bus 0000:00: root bus resource [mem 0x90000000-0xafffffff window] [ 0.431065] pci 0000:00:1c.0: PCI bridge to [bus 01] [ 0.436210] pci 0000:01:00.0: [144d:a80a] type 00 class 0x010802 [ 0.441642] pci 0000:01:00.0: BAR 0: assigned [mem 0x90000000-0x90003fff 64bit] [ 0.447318] pci 0000:00:1c.4: PCI bridge to [bus 02-04] [ 0.451900] pci 0000:02:02.0: bridge window [mem 0xa0100000-0xa01fffff] [ 0.458233] pci 0000:04:00.0: [1de5:1001] type 00 class 0x120000 [ 0.462117] pci 0000:04:00.0: reg 0x10: [mem 0x00000000-0x0fffffff 64bit pref] [ 0.476551] pci 0000:04:00.0: BAR 0: no space for [mem size 0x10000000 64bit pref] [ 0.481990] pci 0000:04:00.0: BAR 0: failed to assign [mem size 0x10000000] [ 0.488412] accel 0000:04:00.0: probe failed with error -12 [ 2.441642] nvme nvme0: 4/0/0 default/read/poll queues [ 2.509377] nvme0n1: p1 p2 / # 1 2 3 4 5 1 The only window there is Everything on this root bus has to fit in 0x9000_0000–0xafff_ffff — 512 MiB. Read this line before you read any BAR line. 2 Firmware already froze the window The bridge down to bus 04 got a 1 MiB window at boot. Nothing behind that bridge can ever be larger, whatever the parent has spare. 3 What the device is asking for reg 0x10 reads back 0x0fff_ffff, so BAR0 wants 256 MiB — 256× the window it must live in. This line is the request, not the result. 4 −12 is −ENOMEM, not a driver bug The resource was never assigned, so pci_iomap() in probe() had nothing to map. Fixing the driver cannot fix this; the window has to grow. 5 The healthy one, for contrast Four lines later nvme got its BAR and its queues. Keep a known-good stretch in the same figure — it is what tells you the log itself is fine.
Fourteen lines of real PCI enumeration, marked up and never retyped. Five badges pin lines to notes; the highlight blocks sit under the glyphs and are positioned from character indices, because every line is pinned to an exact textLength. The story: a 256 MiB BAR behind a bridge window firmware sized at 1 MiB, and the minus twelve that follows. The healthy NVMe lines stay in frame on purpose. 十四行真实的 PCI 枚举输出，只加标注、一个字符不改。五个徽章把行钉到右栏说明；高亮块画在文字下面，位置由字符下标算出来——每行都用 textLength 锁死了字符步进。讲的事：一个 256 MiB 的 BAR 挂在 firmware 只给了 1 MiB 的桥窗口后面，接着就是 -12。正常的 nvme 那几行是故意留在画面里的。
templates/diagrams/struct-graph.svg · 1120 × 560
STRUCT GRAPH · WHICH FIELD HOLDS WHICH POINTER pointer field · every arrow starts here, not at the edge of the box mm->mm_mt maple tree, keyed by vm_start · replaced the VMA list and rbtree in 6.1 slot 0 0x5566_1000+ slot 1 0x5566_9000+ slot 2 0x7ffd_0000+ struct task_struct pid pid_t comm[16] char mm mm_struct * active_mm mm_struct * files files_struct * struct mm_struct mm_users atomic_t mm_count atomic_t pgd → page tables mmap_base unsigned long mm_mt maple_tree map_count int · 42 VMAs struct vm_area_struct vm_start 0x5566_1000 vm_end 0x5566_9000 vm_flags VM_READ|VM_EXEC vm_pgoff 0 vm_file file * vm_ops vm_operations_struct * anon_vma NULL until first COW struct vm_area_struct vm_start 0x5566_9000 vm_end 0x5566_b000 vm_flags VM_READ|VM_WRITE struct vm_area_struct vm_start 0x7ffd_0000 vm_end 0x7ffd_2000 vm_flags VM_GROWSDOWN struct file f_inode inode * f_mapping address_space * f_op file_operations * struct vm_operations_struct .fault filemap_fault .map_pages filemap_map_pages .open / .close NULL field names from include/linux/mm_types.h and sched.h at v6.6 rows are in reading order, not struct offset order
task_struct to mm_struct to the maple tree to three VMAs, with every arrow leaving the field that actually holds the pointer and landing on the target's title bar. Start precise, end whole — that asymmetry is the point. One sibling is drawn in full, the other two keep only what tells them apart. Names checked against include/linux/mm_types.h at v6.6. task_struct → mm_struct → maple tree → 三个 VMA，每根箭头从真正持有指针的那一行出发，落在目标卡片的标题栏上。起点精确到字段、终点是整个对象——这个不对称就是重点。兄弟对象只详画一个，其余只留区分它们的那几行。字段名对过 v6.6 的 include/linux/mm_types.h。
templates/diagrams/bus-fabric.svg · 1120 × 560
BUS FABRIC · TWO RAILS, ONE TRACED READ master slave APB peripheral this read CPU cluster 4 × A78 · AXI master 0 DMA engine 16 ch · AXI master 1 GPU / VPU AXI master 2 AXI4 · 128-bit · AW W B AR R APB · 32-bit 128 32 32 arbiter SRAM 256 KiB · 0x0000_0000 AXI → APB bridge protocol converter USB3 · GbE high-speed IP DDR4 controller 0x8000_0000 · 4 GiB UART0 I2C0 SPI0 GPIO WDT 1 2 3 4 every drop carries its own width; the rail carries the name of the channels riding it rails are a drawing, not a topology claim · a real AXI NoC is switched
Masters above the rail, slaves below, the bridge dropping to a narrower rail with its own peripherals. Each drop carries its width as a slash and a number; the rail carries the names of the channels riding it. One read is traced out solid and back dashed, twelve pixels clear of the rail — at eight it vanished into it. The footer says out loud that rails are a drawing, not a topology claim. 主设备在轨上方、从设备在下方，桥再往下接一条更窄的轨和它自己的外设。每条引下线用斜杠加数字标位宽，轨上写跑在它上面的通道名。一次读事务去程实线、回程虚线，离轨 12 px——8 px 时实测糊进轨里看不见。图脚明写：轨是一种画法，不是拓扑论断。
06 · How to use one怎么用

Paste, prune,
let the tokens work. 贴入、删两样，
剩下交给 token。

Each template previews standalone with an embedded style block and a navy backdrop. On a glass page both are dead weight — the page already provides the classes, the canvas and the light. 每张模板都带一段内嵌样式和一块藏青底，用来单独预览。进了 glass 页面这两样都是累赘——页面本身已经提供了类、画布和光。

T·1

Delete the preview style删掉预览样式

Drop the embedded style block and the background rect when you paste. This page did exactly that for all fourteen. 粘贴时删掉内嵌的 style 块和背景 rect。本页的十四张图就是这么处理的。

T·2

Ink through tokens用 token 上墨

Labels go through the .glass-svg classes, so the same SVG survives the light theme. Hardcoded white text vanishes at noon; hardcoded cyan text dies on white. 标签全部走 .glass-svg 类，同一张 SVG 切到 light 主题原样存活。写死的白字到了白天就消失，写死的 cyan 字在白底上看不清。

T·3

Spend cyan like money把 cyan 当钱花

At most three glow elements per diagram — the flow, the focus, the live marker. Zero is a wireframe; four is a christmas tree. 每张图至多三个发光元素——流向、焦点、live 标记。零个是线稿，四个是圣诞树。

07 · Go deeper更进一步

See them in a real page. 看它们在真实页面里的样子。

The flagship demo redraws three of these genres on the repo's own story — architecture, silicon and a three-remote git flow, all in the same glass. 旗舰 demo 用仓库自己的故事重画了其中三种图型——架构、芯片、三远端 git 协作，全部用同一块玻璃。

Open the flagship demo打开旗舰 demo Templates on GitHubGitHub 上的模板